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# spi_drv.h

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    00001 //***************************************************************************
    00014 //***************************************************************************
    00015
    00016 #ifndef _SPI_DRV_H_
    00017 #define _SPI_DRV_H_
    00018
    00019 /*_____ I N C L U D E S  ___________________________*/
    00020
    00021 #include "config.h"
    00022 /*_____ M A C R O S  ___________________________*/
    00023
    00024 /* SPI CONTROLLER */
    00025
    00026
    00027 #define MSK_SPI_SPIE  0x80
    00028 #define MSK_SPI_SPE   0x40
    00029 #define MSK_SPI_DORD  0x20
    00030 #define MSK_SPI_MSTR  0x10
    00031 #define MSK_SPI_CPOL  0x08
    00032 #define MSK_SPI_CPHA  0x04
    00033 #define MSK_SPI_SPR1  0x02
    00034 #define MSK_SPI_SPR0  0x01
    00035
    00036
    00037 #define MSK_SPI_ENABLE_IT  0x80
    00038 #define MSK_SPI_ENABLE     0x40
    00039 #define MSK_SPI_MASTER_MODE   0x10
    00040 #define MSK_SPI_DOUBLESPEED   0x01
    00041
    00042 #define MSK_SPI_DIV4          0x00
    00043 #define MSK_SPI_DIV16         0x01
    00044 #define MSK_SPI_DIV64         0x02
    00045 #define MSK_SPI_DIV128        0x03
    00046 #define MSK_SPI_CPHA_LEADING     0x00
    00047 #define MSK_SPI_CPHA_TRAILING    0x04
    00048 #define MSK_SPI_CPOL_HIGH     0x08
    00049 #define MSK_SPI_CPOL_LOW      0x00
    00050 #define MSK_SPI_LSBFIRST      0x20
    00051 #define MSK_SPI_MSBFIRST      0x00
    00052 #define MSK_SPI_CONF          0x2F
    00053 #define MSK_SPI_SPIF          0x80
    00054 #define MSK_SPI_MODE       0x0C
    00055 #define MSK_MSTR                0x10
    00056
    00057 /*----- Modes -----*/
    00058 #define SPI_MASTER_MODE_0 (Byte)(MSK_MSTR)
    00059 #define SPI_MASTER_MODE_1 (Byte)(MSK_MSTR|0x04)
    00060 #define SPI_MASTER_MODE_2 (Byte)(MSK_MSTR|0x08)
    00061 #define SPI_MASTER_MODE_3 (Byte)(MSK_MSTR|0x0C)
    00062
    00063 #define SPI_SLAVE_MODE_0  (Byte)0x00
    00064 #define SPI_SLAVE_MODE_1  (Byte)0x04
    00065 #define SPI_SLAVE_MODE_2  (Byte)0x08
    00066 #define SPI_SLAVE_MODE_3  (Byte)0x0C
    00067
    00068 /*----- Bit rates -----*/
    00069 //#define SPI_RATE_0        (Byte)0x00    /* Fper / 2 */
    00070 #define SPI_RATE_1        (Byte)0x00    /* Fper / 4 */
    00071 //#define SPI_RATE_2        (Byte)0x02    /* Fper / 8 */
    00072 #define SPI_RATE_3        (Byte)0x01    /* Fper / 16 */
    00073 //#define SPI_RATE_4        (Byte)0x80    /* Fper / 32 */
    00074 #define SPI_RATE_5        (Byte)0x02    /* Fper / 64 */
    00075 #define SPI_RATE_6        (Byte)0x03    /* Fper / 128 */
    00076
    00077 /*______  D E F I N I T I O N  ___________________________*/
    00078
    00079
    00080 #define Spi_enable()            (SPCR |=MSK_SPI_ENABLE)
    00081 #define Spi_disable()           (SPCR &= ~MSK_SPI_ENABLE)
    00082 #define Spi_enable_it()         (SPCR|= MSK_SPI_ENABLE_IT)
    00083 #define Spi_disable_it()        (SPCR&=~MSK_SPI_ENABLE_IT)
    00084 #define Spi_select_slave_mode() (SPCR&=~MSK_SPI_MASTER_MODE)
    00085 #define Spi_select_master_mode() (SPCR|= MSK_SPI_MASTER_MODE)
    00086 #define Spi_set_mode(mode)      (SPCR &= ~(MSK_SPI_MASTER_MODE|MSK_SPI_MODE )); (SPCR |= mode);Spi_init_bus()
    00087 #define Spi_read_data()         (SPDR)
    00088 #define Spi_get_byte()          (SPDR)
    00089 #define Spi_write_data(ch)      (SPDR=ch);Spi_wait_spif();
    00090 #define Spi_send_byte(ch)       (SPDR=ch);Spi_wait_spif();
    00091 #define Spi_wait_spif()         while ((SPSR & MSK_SPI_SPIF) == 0) /* for any SPI_RATE_x */
    00092 #define Spi_wait_eor()          while ((SPSR & MSK_SPI_SPIF) == 0) /* wait end of reception */
    00093 #define Spi_wait_eot()          while ((SPSR & MSK_SPI_SPIF) == 0) /* wait end of transmission */
    00094 #define Spi_eor()               ((SPSR & MSK_SPI_SPIF) == MSK_SPI_SPIF)/* check end of reception */
    00095 #define Spi_eot()               ((SPSR & MSK_SPI_SPIF) == MSK_SPI_SPIF)/* check end of transmission */
    00096 #define Spi_set_doublespeed()   (SPSR|= MSK_SPI_DOUBLESPEED)
    00097 #define Spi_hw_init(conf)       (SPCR&=~MSK_SPI_CONF, SPCR|=conf)
    00098 #define Spi_get_colision_status() (SPSR&(1<<WCOL))
    00099 #define Spi_get_byte()          (SPDR)
    00100 #define Spi_tx_ready()          (SPSR & (1<<SPIF))
    00101 #define Spi_rx_ready()           Spi_tx_ready()
    00102 #define Spi_init_bus()           ((DDRB |= (1<<DDB2)|(1<<DDB1)))
    00103 #define Spi_disable_ss()
    00104 #define Spi_enble_ss()
    00105
    00106 #define Spi_write_dummy()       (SPDR = 0x00);Spi_wait_spif();
    00107 #define Spi_read_dummy()        (0x00 = SPDR)
    00108 #define Spi_config_speed(config) (SPCR &= ~(MSK_SPI_SPR1|MSK_SPI_SPR0), (SPCR |= config))/*see bit rates for config*/
    00109 //#define Spi_set_rate(rate)      (SPCR &= ~MSK_SPR); (SPCR |= rate);(if (rate == (SPI_RATE_0|SPI_RATE_2|SPI_RATE_4) doublespeed());
    00110
    00111 #ifndef DUMMY
    00112   #error "DUMMY should be define in config.h as free general purpose IO register"
    00113 #endif
    00114 #define Spi_ack_read()          (DUMMY = SPSR)
    00115 #define Spi_ack_write()         (DUMMY = SPDR)
    00116 #define Spi_ack_cmd()           (DUMMY = SPSR)
    00117
    00118
    00119 #endif  /* _SPI_DRV_H_ */
    00120